This invention relates to calculators and more particularly to calculators having sequentially clocked logic operable in an active or in a standby low power dissipation mode, such as described in co-pending application Ser. No. 106,430, filed Dec. 26, 1979 for Turn Off Processor Between Key Strokes, by Graham Tubbs, assigned to the same assignee as the present invention, and co-pending application Ser. No. 106,809, filed Dec. 26, 1979 for Four Mode Microcomputer Power Save Operation, by Jeffrey Teza et al, assigned to the same assignee as the present invention. More specifically, the problem resolved by this invention is how to use minimum required power in an IC with clocked CMOS sequential logic while avoiding random output levels. One solution heretofore used was to remove power to the integrated circuit chip either with an external or an internal switch, such as the integrated on switch of the calculator as described in U.S. Pat. No. 4,115,705, which is assigned to the assignee of the present invention. The problem with this approach is that the circuitry must be reinitialized when power is reapplied. Another approach is to initiate a power up clear sequence upon reapplication of power. However, the power up clear sequences are often faulty since they are usually dependent on an RC time constant which may vary with process variations. A third solution has been to selectively gate on oscillators and clock generators to effect power dissipation control. However, these circuits must also be reinitialized so that the logic is in a predefined state upon reapplication of the clocks.